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| Features * * * * * * * * * * * * 3.0V to 5.5V Operating Range Advanced Low Voltage Electricaly Erasable Programmable Logic Device User Controlled Power Down Pin Option Pin-Controlled Standby Power (10 A Typical) Well-Suited for Battery Powered Systems 10 ns Maximum Propagation Delay CMOS and TTL Compatible Inputs and Outputs Latch Feature Hold Inputs to Previous Logic States Advanced Electrically Erasable Technology Reprogrammable 100% Tested High Reliability CMOS Process 20 Year Data Retention 100 Erase/Write Cycles 2,000V ESD Protection 200 mA Latchup Immunity Commercial and Industrial Temperature Ranges Dual-in-Line and Surface Mount Packages in Standard Pinouts High Performance E2 PLD ATF22LV10C Block Diagram Pin Configurations Pin Name CLK IN I/O VCC PD Function Clock Logic Inputs Bidirectional Buffers (3V to 5.5V) Supply Programmable Power Down CLK/IN IN IN IN/PD IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 TSSOP Top View 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN ATF22LV10C DIP/SOIC PLCC (1) Top view Note: 1. For PLCC, pin 1, 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to 8, 15, and 22. Rev. 0780E/LV10C-E-05/98 Description The ATF22LV10C is a high performance CMOS (Electrically Erasable) Programmable Logic Device (PLD) which utilizes Atmel's proven electrically erasable Flash memory technology. Speeds down to 10 ns and power dissipation as low as 10 A are offered. All speed ranges are specified over the 3.0V to 5.5V range for industrial and commercial temperature ranges. The ATF22LV10C provides a low voltage and user controlled "zero" power CMOS PLD solution. A user-controlled power down feature offers "zero" (5 A typical) standby power. This feature allows the user to manage total system power to meet specific application requirements and enhance reliability, all without sacrificing speed. (The ATF22LV10CZ provides edge-sensing "zero" standby power (10 A typical), as well as low voltage operation. See the ATF22LV10CZ Data Sheet.) The ATF22LV10C is capable of operating at supply voltages down to 3.0V. When the power down pin is active, the device is placed into a zero standby power down mode. When the power down pin is not used or active, the device operates in a full power low voltage mode. Pin "keeper" circuits on input and output pins hold pins to their previous logic levels when idle, which eliminate static power consumed by pull-up resistors. The ATF22LV10C macrocell incorporates a variable product term architecture. Each output is allocated from 8 to 16 product terms which allows highly complex logic functions to be realized. Two additional product terms are included to provide synchronous reset and asynchronous reset. These additional product terms are common to all 10 registers and are automatically cleared upon power up. Register Preload simplifies testing. A Security Fuse prevents unauthorized copying of programmed fuse patterns. Absolute Maximum Ratings* Temperature Under Bias................... -40C to +85C Storage Temperature...................... -65C to +150C Voltage on Any Pin with Respect to Ground......................... -2.0V to +7.0V (1) Voltage on Input Pins with Respect to Ground During Programming.................... -2.0V to +14.0V (1) Programming Voltage with Respect to Ground....................... -2.0V to +14.0V (1) *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V dc, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is Vcc + 0.75V dc, which may overshoot to 7.0V for pulses of less than 20 ns. DC and AC Operating Conditions Commercial Operating Temperature (Case) VCC Power Supply 0C - 70C 3.0V - 5.5V Industrial -40C - 85C 3.0V - 5.5V 2 ATF22LV10C ATF22LV10C Functional Logic Diagram Description The Functional Logic Diagram describes the ATF22LV10C architecture. The ATF22LV10C has 12 inputs and 10 I/O macrocells. Each macrocell can be configured into one of four output configurations: active high/low, registered/combinatorial output. The universal architecture of the ATF22LV10C can be programmed to emulate most 24-pin PAL devices. Unused product terms are automatically disabled by the compiler to decrease power consumption. A Security Fuse, when programmed, protects the contents of the ATF22LV10C. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the Security Fuse. DC Characteristics Symbol Parameter IIL IIH ICC ICC2 ICC3 IPD IOS (1) VIL VIH VOL Input or I/O Low Leakage Current Input or I/O High Leakage Current Power Supply Current, Standby Clocked Power Supply Current Clocked Power Supply Current Power Supply Current, PD Mode Output Short Circuit Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VIN = VIH or VIL VCC = MIN, IOL = 8 mA VIN = VIH or VIL, VCC = MIN, IOH = -4.0 mA 2.4 Condition 0 VIN VIL(max) (VCC - 0.2)V VIN VCC VCC = MAX, VIN = MAX, Outputs Open VCC = MAX, Outputs Open VCC = MAX, Outputs Open, f = 15 MHz VCC = MAX, VIN = MAX, Outputs Open VOUT = 0.5V -0.5 2.0 Com. Ind. Com. Ind. Com. Ind. Com. Ind. 10 10 55 60 1 1 100 105 100 100 -130 0.8 VCC + 0.75 0.5 Min Typ Max -10 10 85 90 Units A A mA mA mA/MHz mA/MHz mA mA A A mA V V V V VOH Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 3 AC Waveforms AC Characteristics (1) -10 Symbol tPD tCF tCO tS tH tP tW FMAX tEA tER tAP tSP tAW tAR tSPR Note: -15 Max Min Max Parameter Input to Feedback to Non-Registered Output Clock to Feedback Clock to Output Input or Feedback Setup Time Input Hold Time Clock Period Clock Width External Feedback 1/(tS + tCO) Internal Feedback 1/(tS + tCF) No Feedback 1/(tP) Input to Output Enable Input to Output Disable Input or I/O to Asynchronous Reset of Register Setup Time, Synchronous Preset Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset to Clock Recovery Time Min Units ns ns ns ns ns ns ns 3 2 7.5 0 12 6 10 5 6.5 3 2 12 0 16 8 15 8 10 71.4 80 83.3 3 2 3 10 8 6 10 12 12 13 3 2 3 10 8 6 10 45.5 50 62.5 15 15 15 MHz MHz MHz ns ns ns ns ns ns ns 1. See ordering information for valid part numbers. 4 ATF22LV10C ATF22LV10C Power Down AC Characteristics -10 Symbol tIVDH tGVDH tCVDH tDHIX tDHGX tDHCX tDLIV tDLGV tDLCV tDLOV Parameter Valid Input Before PD High Valid OE Before PD High Valid Clock Before PD High Input Don't Care After PD High OE Don't Care After PD High Clock Don't Care After PD High PD Low to Valid Input PD Low to Valid OE PD Low to Valid Clock PD Low to Valid Output MIn Max Min -15 Max Units ns ns ns 10 0 0 10 10 10 5 3 10 7.5 15 0 0 15 15 15 7.5 3 10 7.5 ns ns ns ns ns ns ns Input Test Waveforms and Measurement Levels Output Test Loads Note: Similar competitors' devices are specified with slightly different loads. These load differences may affect output signals' delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification conditions. Pin Capacitance (f = 1 MHz, T = 25C) Typ CIN COUT Note: Max 8 8 Units pF pF Conditions VIN = 0V VOUT = 0V 5 6 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 5 Power Up Reset The registers in the ATF22LV10C are designed to reset during power up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic and start below 0.7V. 2. The clock must remain stable during TPR. 3. After TPR, all input and feedback setup times must be met before driving the clock pin high. file preload sequence will be done automatically by most of the approved programmers after the programming. Electronic Signature Word There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF22LV10C fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. Preload of Register Outputs The ATF22LV10C's registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC Programming/Erasing Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware & Software Support for information on software/programming. Parameter TPR VRST Description Power-Up Reset Time Power-Up Reset Voltage Typ 600 2.5 Max 1,000 3.0 Units ns V 6 ATF22LV10C ATF22LV10C Input and I/O Pin Keeper All ATF22V10C family members have internal input and I/O pin-keeper circuits. Therefore, whenever inputs or I/Os are not being driven externally, they will maintain their last driven state. This ensures that all logic array inputs and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by TTL-compatible drivers (see input and I/O diagrams below). of power down will remain at the same state. During power down, all input signals except the power down pin are blocked. Input and I/O hold latches remain active to insure that pins do not float to indeterminate levels, further reducing system power. The power down pin feature is enabled in the logic design file. Designs using the power down pin may not use the PD pin logic array input. However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback product term array inputs. PD pin configuration is controlled by the design file, and appears as a separate fuse bit in the JEDEC file. When the power down feature is not specified in the design file, the IN/PD pin will be configured as a regular logic input. Note: Some programmers list the 22V10 JEDEC compatible 22V10C (no PD used) separately from the non-22V10 JEDEC compatible 22V10CEX (with PD used). Power Down Mode The ATF22LV10C includes an optional pin controlled power down feature. When this mode is enabled, the PD pin acts as the power down pin (Pin 4 on the DIP/SOIC packages and Pin 5 on the PLCC package). When the PD pin is high, the device supply current is reduced to less than 100 A. During power down, all output data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs which were in an undetermined state at the onset Input Diagram I/O Diagram 7 Functional Logic Diagram ATF22LV10C * Input not available if the power down (PD) option is utilized. 8 ATF22LV10C ATF22LV10C tPD (ns) 10 tS (ns) 7.5 tCO (ns) 6.5 Ordering Code ATF22LV10C-10JC ATF22LV10C-10PC ATF22LV10C-10SC ATF22LV10C-10XC ATF22LV10C-15JC ATF22LV10C-15PC ATF22LV10C-15SC ATF22LV10C-15XC ATF22LV10C-15JI ATF22LV10C-15PI ATF22LV10C-15SI ATF22LV10C-15XI Package 28J 24P3 24S 24X 28J 24P3 24S 24X 28J 24P3 24S 24X Operation Range Commercial (0C to 70C) 15 12 10 Commercial (0C to 70C) 12 10 Industrial (-40C to +85C) Package Type 28J 24P3 24S 24X 28-Lead, Plastic J-Leaded Chip Carrier (PLCC) 24-Lead, 0.300" Wide, Plastic Dual Inline Package (DIP) 24-Lead, 0.300" Wide, Plastic Gull WIng Small Outline (SOIC) 24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline TSSOP 9 |
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